1. Field of the Invention
The present invention is directed to a processor or microcontroller in which scheduled changes in program flow, such as which is to occur due to a branch instruction, are to a target address aligned on a word boundary, variable size instructions can be aligned on a byte boundary and nonscheduled program flow changes, such as interrupt returns and returns from a procedure are to a byte aligned point and, more particularly, to a system in which instructions can be a selected number of bytes in length and are aligned on byte boundaries except when the instruction is at a target address of a branch instruction in which case it is aligned on a word boundary.
2. Description of the Related Art
Instruction sets for different processors define the permissible addresses of each data item or first byte of any instruction. Known processors can be divided into 2 categories: 1) Fully-aligned where the address can be only on specific boundaries, normally byte, word (for example, 2-bytes) or doubleword (for example, 4-bytes). These processors implement an instruction set with (binary) instruction size as a multiple of their alignment size. 2) Non-aligned where the address is not restricted to any size alignment, i.e., it could start at any (permissible) address granularity, normally at, but not necessarily limited to, any byte address.
One factor that is of interest for performance evaluation of processors or microcontrollers, is the way code is read from the memory system, including caching schemes, read-write memory and read-only memory. Due to the high-speed of internal execution and the resulting increased instruction bandwidth requirements of today's processors and microcontrollers, memories are commonly accessed through multi-byte buses (or data paths). The simplest way to handle the high-speed access and avoid unnecessary gate delays is to access the memory at a fixed alignment for each code or instruction read. This avoids a complex, post fetch alignment scheme at most (or all) levels of the system hierarchy. This approach is universally accepted in high-performance or multi-byte oriented processor implementations. It works particularly well for the fully-aligned architectures discussed above. For those processors which implement the non-aligned approach, code fetches after a branch to a non-aligned address usually take extra memory cycles (when the target instruction length crosses the aligned memory access boundary). This has a major drawback of slowing down the execution and degrading processor performance. There are several solutions to this problem, most of which implement some type of caching scheme, which is relatively expensive. The most desirable approach, for the simplicity of the code fetch and instruction alignment is the fully-aligned instruction set.
Another factor of interest in today's microcontrollers is code density. Each instruction has a quantifiable amount of information and requires a certain size to contain all the needed information. There are many ways to optimize the encoding of each instruction for a particular technology/architecture. In general, they follow a very simple rule: the most frequently used instructions should be as short as possible, cutting on bandwidth (dynamic code size) and code memory size (static code size) requirements. The impact of the encoding is influenced by many factors, but for the cost driven design this rule holds very well and tends to increase program code density. Following that rule may dictate variable size instructions, possibly at non-aligned addresses. For simple cost driven processor designs, the fully-aligned approach will increase code size slightly but increase performance due to the reduced branch penalty, while the non-aligned approach will reduce code size with a performance degradation.
What is needed is an optimal solution that takes advantage of the code packing density of the non-aligned architecture and of the fetch speed and simplicity of the fully aligned architecture.